Invention Grant
- Patent Title: System and method for synthesis of a network-on-chip to determine optimal path with load balancing
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Application No.: US16845056Application Date: 2020-04-09
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Publication No.: US11418448B2Publication Date: 2022-08-16
- Inventor: Youcef Bourai , Syed Ijlal Ali Shah , Khaled Labib
- Applicant: ARTERIS, INC.
- Applicant Address: US CA Campbell
- Assignee: ARTERIS, INC.
- Current Assignee: ARTERIS, INC.
- Current Assignee Address: US CA Campbell
- Agency: Dana Legal Services
- Agent Jubin Dana
- Main IPC: H04W4/00
- IPC: H04W4/00 ; H04L47/125 ; H04L45/121 ; H04L45/24 ; H04L45/128

Abstract:
A system, and corresponding method, is described for finding the optimal or the best set of routes from a master to each of its connected slaves, for all the masters and slaves using a Network-on-Chip (NoC). More precisely, some embodiments of the invention apply to a class of NoCs that utilize a two-dimensional mesh topology, wherein a set of switches are arranged on a two-dimensional grid. Masters (initiators or sources) inject data packets or traffic into the NoC. Slaves (targets or destinations) service the data packets or traffic traveling through the NoC. The NoC includes switches and links. Additionally, the optimal routes defined by the system includes moving the traffic in a way that avoids deadlock scenarios.
Public/Granted literature
- US20210320869A1 SYSTEM AND METHOD FOR SYNTHESIS OF A NETWORK-ON-CHIP TO DETERMINE OPTIMAL PATH WITH LOAD BALANCING Public/Granted day:2021-10-14
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