Invention Grant
- Patent Title: Multilayer flex circuit with non-plated outer metal layer
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Application No.: US16824269Application Date: 2020-03-19
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Publication No.: US11419213B2Publication Date: 2022-08-16
- Inventor: Nobumasa Nishiyama , Teruhiro Nakamiya , Satoshi Nakamura , Hiroshi Matsuda
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Kunzler Bean & Adamson
- Main IPC: H05K1/00
- IPC: H05K1/00 ; H05K1/02 ; H05K1/03 ; H05K1/09 ; H05K1/11 ; H05K1/14 ; H05K3/32 ; H05K3/36 ; H05K3/38 ; H05K3/40 ; H05K3/46 ; H01L21/20 ; H01L23/00 ; H01L23/48 ; H05K3/42 ; G11B5/48

Abstract:
Described herein is a multilayer flex circuit having a first dual flex circuit and a second dual flex circuit where each one comprises an outer metal layer, a base insulation layer, and an inner metal layer. The base insulation layer is disposed between the outer metal layer and the inner metal layer. The inner metal layer of the first dual flex circuit is configured to face toward the inner metal layer of the second dual flex circuit. The multilayer flex circuit also includes a coupling layer that adhesively couples the inner metal layer of the first dual flex circuit to the inner metal layer of the second dual flex circuit. The multilayer flex circuit also comprises an electrically conductive material that electrically connects the inner metal layer of the second dual flex circuit to the inner metal layer of the first dual flex circuit.
Public/Granted literature
- US20200315014A1 MULTILAYER FLEX CIRCUIT WITH NON-PLATED OUTER METAL LAYER Public/Granted day:2020-10-01
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