- Patent Title: Semiconductor memory device having a first plane and a second plane including respective latch circuits, and first and second FIFO circuits for fetching read data from the latch circuits
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Application No.: US17164273Application Date: 2021-02-01
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Publication No.: US11423958B2Publication Date: 2022-08-23
- Inventor: Akio Sugahara
- Applicant: Kioxia Corporation
- Applicant Address: JP Tokyo
- Assignee: Kioxia Corporation
- Current Assignee: Kioxia Corporation
- Current Assignee Address: JP Tokyo
- Agency: Holtz, Holtz & Volek PC
- Priority: JPJP2020-077627 20200424
- Main IPC: G11C7/10
- IPC: G11C7/10
Abstract:
According to one embodiment, a semiconductor memory device includes: a first plane PL0 including a first memory cell array 57A, and a first latch circuit 60A configured to store first read data read from the first memory cell array 57A; a second plane PL1 including a second memory cell array 57B, and a second latch circuit 60B configured to store second read data read from the second memory cell array 57B; and an I/O circuit 11 including a first FIFO circuit 14A configured to fetch the first read data from the first latch circuit 60A, and a second FIFO circuit 14B configured to fetch the second read data from the second latch circuit 60B.
Public/Granted literature
- US20210335398A1 SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2021-10-28
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