In certain embodiments, a method for designing a semiconductor device includes generating a two-dimensional design for fabricating chiplets on a semiconductor substrate. The chiplets are component levels for a multi-chip integrated circuit. The two-dimensional design includes a first layout for alignment features and semiconductor structures to be formed on a first surface of a first chiplet and a second layout for alignment features and semiconductor structures to be formed on a first surface of a second chiplet. The second chiplet is adjacent to the first chiplet on the semiconductor substrate. The second layout is a mirror image of the first layout across a reference line shared by the first chiplet and the second chiplet. The first surface of the first chiplet and the first surface of the second chiplet are both either top surfaces or bottom surfaces. The method further includes generating a photomask according to the design.