- Patent Title: Self-aligned gate endcap (SAGE) architecture having gate contacts
-
Application No.: US16294210Application Date: 2019-03-06
-
Publication No.: US11424245B2Publication Date: 2022-08-23
- Inventor: Sairam Subramanian , Walid M. Hafez
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt P.C.
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/94 ; H01L31/062 ; H01L27/092 ; H01L29/78 ; H01L21/8238 ; H01L29/66 ; H01L21/768

Abstract:
Self-aligned gate endcap (SAGE) architectures having gate contacts, and methods of fabricating SAGE architectures having gate contacts, are described. In an example, an integrated circuit structure includes a gate structure over a semiconductor fin. A gate endcap isolation structure is laterally adjacent to and in contact with the gate structure. A trench contact structure is over the semiconductor fin, where the gate endcap isolation structure is laterally adjacent to and in contact with the trench contact structure. A local gate-to-contact interconnect is electrically connecting the gate structure to the trench contact structure.
Public/Granted literature
- US20200286890A1 SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURE HAVING GATE CONTACTS Public/Granted day:2020-09-10
Information query
IPC分类: