Invention Grant
- Patent Title: Method of fabricating vertical memory device
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Application No.: US17159979Application Date: 2021-01-27
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Publication No.: US11424269B2Publication Date: 2022-08-23
- Inventor: Jae Gil Lee , Ju Ry Song , Hyangkeun Yoo , Se Ho Lee
- Applicant: SK hynix Inc.
- Applicant Address: KR Icheon-si
- Assignee: SK hynix Inc.
- Current Assignee: SK hynix Inc.
- Current Assignee Address: KR Icheon-si
- Priority: KR10-2018-0171070 20181227
- Main IPC: H01L27/11597
- IPC: H01L27/11597 ; H01L29/423 ; H01L29/417 ; H01L29/51 ; H01L29/66 ; H01L29/78 ; H01L21/28

Abstract:
In a method, a stack structure including a plurality of first interlayer sacrificial layers and a plurality of second interlayer sacrificial layers that are alternately stacked is formed over a substrate. A trench penetrating the stack structure is formed. A channel layer covering a sidewall surface of the trench is formed. The plurality of first interlayer sacrificial layers are selectively removed to form a plurality of first recesses. The plurality of first recesses are filled with a conductive material to form a plurality of channel contact electrode layers. The plurality of second interlayer sacrificial layers are selectively removed to form a plurality of second recesses. A plurality of interfacial insulation layers, a plurality of ferroelectric layers and a plurality of gate electrode layers are formed in the plurality of second recesses.
Public/Granted literature
- US20210183890A1 METHOD OF FABRICATING VERTICAL MEMORY DEVICE Public/Granted day:2021-06-17
Information query
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