Invention Grant
- Patent Title: Static data bus address allocation
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Application No.: US15061010Application Date: 2016-03-04
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Publication No.: US11424952B2Publication Date: 2022-08-23
- Inventor: Peter Vandersteegen
- Applicant: MELEXIS TECHNOLOGIES NV
- Applicant Address: BE Tessenderlo
- Assignee: MELEXIS TECHNOLOGIES NV
- Current Assignee: MELEXIS TECHNOLOGIES NV
- Current Assignee Address: BE Tessenderlo
- Agency: Workman Nydegger
- Priority: GB1503801 20150306
- Main IPC: G06F13/42
- IPC: G06F13/42 ; H04L12/40 ; H04L61/5038 ; G06F13/40 ; H04L101/627

Abstract:
The present invention relates to a data bus node integrated circuit comprising at least one static address selection terminal and a detecting circuit for detecting a state of the address selection terminal. The IC also comprises a communication circuit for data communication over a data bus. This circuit is adapted for determining a node address identifier taking the detected state of the at least one static address selection terminal into account. The detecting circuit is adapted for detecting the state of the address selection terminal by determining whether the address selection terminal is in a floating state, a power supply voltage state or a ground voltage state.
Public/Granted literature
- US20160261426A1 STATIC DATA BUS ADDRESS ALLOCATION Public/Granted day:2016-09-08
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