Invention Grant
- Patent Title: Error unbiased approximate multiplier for normalized floating-point numbers and implementation method of error unbiased approximate multiplier
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Application No.: US17190417Application Date: 2021-03-03
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Publication No.: US11429347B2Publication Date: 2022-08-30
- Inventor: Cheng Zhuo , Chuangtao Chen , Sen Yang
- Applicant: ZHEJIANG UNIVERSITY
- Applicant Address: CN Zhejiang
- Assignee: ZHEJIANG UNIVERSITY
- Current Assignee: ZHEJIANG UNIVERSITY
- Current Assignee Address: CN Zhejiang
- Agency: JCIP Global Inc.
- Priority: CN202010969041.7 20200915
- Main IPC: G06F7/487
- IPC: G06F7/487

Abstract:
The present invention discloses an error unbiased approximate multiplier for normalized floating-point numbers and an implementation method of the error unbiased approximate multiplier. The error unbiased approximate multiplier includes a symbol and exponent bit module, a mantissa approximation module and a normalization module, wherein the symbol and exponent bit module processes symbolic operation and exponent bit operation of the floating-point numbers; the mantissa approximation module obtains a mantissa approximation result under different accuracy requirements by summing a result of multilevel error correction modules; and the normalization module adjusts an exponent bit according to the operation result of the mantissa and processes the overflow of the exponent bit to obtain the final product result. According to the present invention, for the multiply operation of the normalized floating-point numbers under the IEEE 754 standard, under the controllable accuracy levels, error distribution is unbiased, and area, speed and energy efficiency are obviously improved.
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