- Patent Title: Methods of forming memory devices including stair step structures
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Application No.: US17134930Application Date: 2020-12-28
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Publication No.: US11430734B2Publication Date: 2022-08-30
- Inventor: Paolo Tessariol , Graham R. Wolstenholme , Aaron Yip
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: TraskBritt
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/528 ; H01L23/522 ; H01L27/11575 ; H01L27/11524 ; H01L27/1157 ; H01L27/11517 ; H01L27/11548
Abstract:
Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.
Public/Granted literature
- US20210151375A1 METHODS OF FORMING MEMORY DEVICES INCLUDING STAIR STEP STRUCTURES Public/Granted day:2021-05-20
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