Invention Grant
- Patent Title: Systems and methods for predictive scheduling and rate limiting
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Application No.: US17093200Application Date: 2020-11-09
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Publication No.: US11431646B2Publication Date: 2022-08-30
- Inventor: Kulwinder Singh Dhanoa
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Fletcher Yoder, P.C.
- Main IPC: H04L47/50
- IPC: H04L47/50 ; H04L47/52 ; H04L47/628 ; H04L47/62 ; H04L47/80 ; H04L47/36 ; H04L67/61 ; H04L47/10

Abstract:
Systems and methods are disclosed for enhancing network performance by using modified traffic control (e.g., rate limiting and/or scheduling) techniques to control a rate of packet (e.g., data packet) traffic to a queue scheduled by a Quality of Service (QoS) engine for reading and transmission. In particular, the QoS engine schedules packets using estimated packet sizes before an actual packet size is known by a direct memory access (DMA) engine coupled to the QoS engine. The QoS engine subsequently compensates for discrepancies between the estimated packet sizes and actual packet sizes (e.g., when the DMA engine has received an actual packet size of the scheduled packet). Using these modified traffic control techniques that leverage estimating packet sizes may reduce and/or eliminate latency introduced due to determining actual packet sizes.
Public/Granted literature
- US20210083986A1 SYSTEMS AND METHODS FOR PREDICTIVE SCHEDULING AND RATE LIMITING Public/Granted day:2021-03-18
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