A memory controller is able to issue a first write command for writing data of a predetermined length into a DRAM and a second write command for writing data which is less than the predetermined length in the DRAM. The memory controller includes a deciding unit configured to decide an issuance order of one or more requests stored in a storage unit. In a period from the issuance of a preceding DRAM command until a second write command targeting the same bank as the preceding DRAM command is issued, if another DRAM command targeting a bank different from the bank targeted by the preceding DRAM command can be issued, the deciding unit will decide the issuance order so that the other DRAM command that can be issued will be issued before the second write command.