Invention Grant
- Patent Title: NAND parity information techniques for systems with limited RAM
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Application No.: US17228425Application Date: 2021-04-12
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Publication No.: US11436078B2Publication Date: 2022-09-06
- Inventor: Harish Reddy Singidi , Xiangang Luo , Jianmin Huang , Kishore Kumar Muchherla , Ashutosh Malshe , Vamsi Pavan Rayaprolu , Sampath Ratnam
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F11/10
- IPC: G06F11/10 ; G11C7/10 ; G11C11/419 ; G06F12/02

Abstract:
Disclosed in some examples are techniques for handling parity data of a non-volatile memory device with limited cache memory. In certain examples, user data can be programmed into the non-volatile memory of the non-volatile memory device in data stripes, and parity information can be calculated for each individual data stripe within a limited capacity cache of the non-volatile memory device. The individual parity information can be swapped between a swap block of the non-volatile memory and the limited capacity cache as additional data stripes are programmed.
Public/Granted literature
- US20210303394A1 NAND PARITY INFORMATION TECHNIQUES FOR SYSTEMS WITH LIMITED RAM Public/Granted day:2021-09-30
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