Invention Grant
- Patent Title: Semiconductor device, sintered metal sheet, and method for manufacturing sintered metal sheet
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Application No.: US17261715Application Date: 2019-03-20
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Publication No.: US11437338B2Publication Date: 2022-09-06
- Inventor: Tomohisa Suzuki , Hiroshi Moriya
- Applicant: HITACHI, LTD.
- Applicant Address: JP Tokyo
- Assignee: HITACHI, LTD.
- Current Assignee: HITACHI, LTD.
- Current Assignee Address: JP Tokyo
- Agent Volpe Koenig
- Priority: JPJP2018-142168 20180730
- International Application: PCT/JP2019/011935 WO 20190320
- International Announcement: WO2020/026516 WO 20200206
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/373

Abstract:
A method utilized at a sintered metal layer bonding a semiconductor element and a support substrate together suppresses cracks appearing in the sintered metal layer, and damage to the semiconductor element. A semiconductor device includes a support substrate, a semiconductor element, and a sintered metal layer bonding the support substrate and the semiconductor element. The sintered metal layer has a low porosity region disposed inward of an outer edge of the semiconductor element with the sintered metal layer bonded to the semiconductor element. The region is lower in porosity than the remaining sintered metal layer, and is formed as a wall-shaped structural body having an elongated string and extending from an upper surface to a lower surface of the sintered metal layer. The low porosity region is disposed to surround a region immediately below a center of the semiconductor element along the outer edge of the semiconductor element.
Public/Granted literature
- US20210265298A1 SEMICONDUCTOR DEVICE, SINTERED METAL SHEET, AND METHOD FOR MANUFACTURING SINTERED METAL SHEET Public/Granted day:2021-08-26
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