Invention Grant
- Patent Title: Transistors stacked on front-end p-type transistors
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Application No.: US16024696Application Date: 2018-06-29
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Publication No.: US11437405B2Publication Date: 2022-09-06
- Inventor: Gilbert Dewey , Patrick Morrow , Aaron Lilak , Willy Rachmady , Anh Phan , Ehren Mannebach , Hui Jae Yoo , Abhishek Sharma , Van H. Le , Cheng-Ying Huang
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe Williamson & Wyatt P.C.
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L27/12 ; H01L21/82 ; H01L29/786 ; H01L21/8258
Abstract:
Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a first transistor, an insulator layer above the first transistor, and a second transistor above the insulator layer. The first transistor may be a p-type transistor including a channel in a substrate, a first source electrode, and a first drain electrode. A first metal contact may be coupled to the first source electrode, while a second metal contact may be coupled to the first drain electrode. The insulator layer may be next to the first metal contact, and next to the second metal contact. The second transistor may include a second source electrode, and a second drain electrode. The second source electrode may be coupled to the first metal contact, or the second drain electrode may be coupled to the second metal contact. Other embodiments may be described and/or claimed.
Public/Granted literature
- US20200006388A1 TRANSISTORS STACKED ON FRONT-END P-TYPE TRANSISTORS Public/Granted day:2020-01-02
Information query
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