- Patent Title: Fluorine-free interface for semiconductor device performance gain
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Application No.: US17225835Application Date: 2021-04-08
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Publication No.: US11437477B1Publication Date: 2022-09-06
- Inventor: Yu-Ting Tsai , Chung-Liang Cheng , Hong-Ming Lo , Chun-Chih Lin , Chyi-Tsong Ni
- Applicant: Taiwan Semiconductor Manufacturing Company Limited
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company Limited
- Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
- Current Assignee Address: TW Hsinchu
- Agency: Harrity & Harrity, LLP
- Main IPC: H01L21/82
- IPC: H01L21/82 ; H01L29/417 ; H01L29/40 ; H01L29/49 ; H01L29/423 ; H01L29/45

Abstract:
A semiconductor may include an active region, an epitaxial source/drain formed in and extending above the active region, and a first dielectric layer formed over a portion of the active region. The semiconductor may include a first metal gate and a second metal gate formed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer and the second metal gate, and a titanium layer, without an intervening fluorine residual layer, formed on the metal gate and the epitaxial source/drain. The semiconductor may include a first metal layer formed on top of the titanium layer on the first metal gate, a second metal layer formed on top of the titanium layer on the epitaxial source/drain, and a third dielectric layer formed on the second dielectric layer. The semiconductor may include first and second vias formed in the third dielectric layer.
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