A phase locked loop (PLL) comprises: a reference oscillator to generate a reference clock having a reference frequency; a voltage controlled oscillator (VCO) to generate a VCO clock having a VCO frequency controlled in response to a control signal applied to the VCO; a first integrator to integrate the reference frequency into a first ramp slope; a second integrator to integrate the VCO frequency into a second ramp slope; and a slope comparator to generate a slope difference between the first ramp slope and the second ramp slope and that is conveyed by the control signal, such that the control signal is configured to drive the VCO frequency toward the reference frequency to minimize the slope difference and frequency lock the VCO frequency to the reference frequency.