Invention Grant
- Patent Title: Failure-tolerant error correction layout for memory sub-systems
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Application No.: US16205075Application Date: 2018-11-29
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Publication No.: US11438012B2Publication Date: 2022-09-06
- Inventor: Wei Wu , Zhenlei Shen , Zhengang Chen
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- Main IPC: H03M13/15
- IPC: H03M13/15 ; G06F11/10
Abstract:
Codewords of an error correcting code can be received. The codewords can be separated into multiple segments. The segments of the codewords can be distributed in an error correcting layout across a plurality of dies where at least a portion of the error correcting layout constitutes a Latin Square (LS) layout.
Public/Granted literature
- US20200177205A1 FAILURE-TOLERANT ERROR CORRECTION LAYOUT FOR MEMORY SUB-SYSTEMS Public/Granted day:2020-06-04
Information query
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