Invention Grant
- Patent Title: Integrated circuit package and method
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Application No.: US17162073Application Date: 2021-01-29
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Publication No.: US11450581B2Publication Date: 2022-09-20
- Inventor: Teng-Yuan Lo , Lipu Kris Chuang , Hsin-Yu Pan
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/24
- IPC: H01L23/24 ; H01L25/00 ; H01L23/00 ; H01L25/065 ; H01L23/31 ; H01L23/498 ; H01L25/10 ; H01L21/48 ; H01L21/56

Abstract:
A package structure and a method of forming the same are provided. A method includes forming first electrical connectors and second electrical connectors on a first side of an interposer wafer. An integrated circuit die is bonded to the first side of the interposer wafer using the first electrical connectors. A stiffener structure is attached to the first side of the interposer wafer adjacent the integrated circuit die. The stiffener structure covers the second electrical connectors in a plan view. The integrated circuit die and the stiffener structure are encapsulated with a first encapsulant. The interposer wafer and the stiffener structure are singulated to form a stacked structure.
Public/Granted literature
- US20220068736A1 INTEGRATED CIRCUIT PACKAGE AND METHOD Public/Granted day:2022-03-03
Information query
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