Invention Grant
- Patent Title: Arrangement of bond pads on an integrated circuit chip
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Application No.: US17175275Application Date: 2021-02-12
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Publication No.: US11450635B2Publication Date: 2022-09-20
- Inventor: Chia-Chi Hsu
- Applicant: Changxin Memory Technologies, Inc.
- Applicant Address: CN Anhui
- Assignee: Changxin Memory Technologies, Inc.
- Current Assignee: Changxin Memory Technologies, Inc.
- Current Assignee Address: CN Anhui
- Agency: Sheppard Mullin Richter & Hampton LLP
- Priority: CN201811011188.4 20180831,CN201821427834.0 20180831
- Main IPC: H01L23/00
- IPC: H01L23/00
Abstract:
The embodiments of the present invention discloses an arrangement of bond pads on an integrated circuit chip. The integrated circuit chip includes: a first row of bond pads; and a second row of bond pads, wherein bond pads in the first row are positioned alternately with bond pads in the second row, and a short side of the bond pads in the first row and the second row is parallel to a long side of the integrated circuit chip. With this arrangement of bond pads on the integrated circuit chip, the bond pads may occupy a reduced area of a surface of the integrated circuit chip.
Public/Granted literature
- US20210167028A1 ARRANGEMENT OF BOND PADS ON AN INTEGRATED CIRCUIT CHIP Public/Granted day:2021-06-03
Information query
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