Invention Grant
- Patent Title: Method for manufacturing multilayer printed wiring board
-
Application No.: US16632790Application Date: 2018-07-25
-
Publication No.: US11452216B2Publication Date: 2022-09-20
- Inventor: Kazuki Matsumura , Yohsuke Ishikawa , Koji Kishino
- Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
- Applicant Address: JP Osaka
- Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
- Current Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
- Current Assignee Address: JP Osaka
- Agency: Greenblum & Bernstein, P.L.C.
- Priority: JPJP2017-144010 20170725
- International Application: PCT/JP2018/027794 WO 20180725
- International Announcement: WO2019/022101 WO 20190131
- Main IPC: H05K3/46
- IPC: H05K3/46 ; C09J7/35 ; C09J7/10 ; B32B15/02 ; B32B15/092 ; B32B15/20 ; B32B27/20 ; B32B27/38 ; B32B37/06 ; B32B37/10 ; C09J5/06 ; C09J11/02 ; B29C70/42 ; B29K63/00 ; B29L31/34

Abstract:
A first stack is formed by stacking a first sheet of metal foil, a first prepreg, and a second sheet of metal foil, one on top of another. The first prepreg is thermally cured by thermally pressing these members to make a double-sided metal-clad laminate. Conductor wiring is formed by partially removing the first sheet of metal foil from the double-sided metal-clad laminate to make a printed wiring board. After a third sheet of metal foil has been preheated, the conductor wiring of the printed wiring board, a second prepreg, and the third sheet of metal foil are stacked one on top of another and thermally pressed together. The first insulating layer has a lower linear expansion coefficient than any of the first sheet of metal foil or the second sheet of metal foil does.
Public/Granted literature
- US20210161020A1 METHOD FOR MANUFACTURING MULTILAYER PRINTED WIRING BOARD Public/Granted day:2021-05-27
Information query