Invention Grant
- Patent Title: Distributed grouped terminations for multiple memory integrated circuit systems
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Application No.: US16916945Application Date: 2020-06-30
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Publication No.: US11456022B2Publication Date: 2022-09-27
- Inventor: John Thomas Contreras , Srinivas Rajendra , Sayed Mobin , Rehan Ahmed Zakai
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Patterson + Sheridan, LLP
- Agent Steven H. VerSteeg
- Main IPC: G11C16/04
- IPC: G11C16/04 ; G11C7/10 ; H03K19/00 ; H01L25/065 ; G06F3/06

Abstract:
The present disclosure generally relates to apparatuses and methods for transmission line termination. In one embodiment an apparatus includes a stack of uniform memory dies and a storage controller. Each uniform memory die in the stack of uniform memory dies couples to a transmission line in series through wire bonds to form a transmission path. Each memory die includes an on-die termination resistance circuit connected to the transmission line. The on-die termination resistance circuit provides a minimum termination resistance. The storage controller addresses a target uniform memory die of the stack of uniform memory dies for an operation. The storage controller enables the on-die termination resistance circuits of a plurality of uniform memory dies along the transmission path. The storage controller transmits a data signal for the operation to the target uniform memory die with the on-die termination resistance circuit enabled for the plurality of uniform memory dies.
Public/Granted literature
- US20210407565A1 DISTRIBUTED GROUPED TERMINATIONS FOR MULTIPLE MEMORY INTEGRATED CIRCUIT SYSTEMS Public/Granted day:2021-12-30
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