Invention Grant
- Patent Title: Method of lapping semiconductor wafer and semiconductor wafer
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Application No.: US16324291Application Date: 2017-05-01
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Publication No.: US11456168B2Publication Date: 2022-09-27
- Inventor: Daisuke Hashimoto , Satoshi Matagawa , Tomohiro Hashii
- Applicant: SUMCO CORPORATION
- Applicant Address: JP Tokyo
- Assignee: SUMCO CORPORATION
- Current Assignee: SUMCO CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Greenblum & Bernstein, P.L.C.
- Priority: JPJP2016-169383 20160831
- International Application: PCT/JP2017/017201 WO 20170501
- International Announcement: WO2018/042761 WO 20180308
- Main IPC: B24B37/08
- IPC: B24B37/08 ; B24B37/28 ; H01L21/02 ; H01L21/304 ; B24B37/04 ; H01L29/16 ; H01L29/34

Abstract:
Provided is a method of lapping a semiconductor wafer, which can suppress the formation of a ring-shaped pattern in a nanotopography map. The method of lapping a semiconductor wafer includes: a stopping step of stopping lapping of a semiconductor wafer; a reversing step of reversing surfaces of the semiconductor wafer facing a upper plate and a lower plate after the stopping step; and a resuming step of resuming lapping of the semiconductor wafer after the reversing step while maintaining the reversal of the surfaces facing the plates.
Public/Granted literature
- US20190181001A1 METHOD OF LAPPING SEMICONDUCTOR WAFER AND SEMICONDUCTOR WAFER Public/Granted day:2019-06-13
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