Invention Grant
- Patent Title: Operational amplifier with reduced input capacitance
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Application No.: US17565370Application Date: 2021-12-29
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Publication No.: US11456715B1Publication Date: 2022-09-27
- Inventor: Yutaka Saeki
- Applicant: Synaptics Incorporated
- Applicant Address: US CA San Jose
- Assignee: Synaptics Incorporated
- Current Assignee: Synaptics Incorporated
- Current Assignee Address: US CA San Jose
- Agency: Ferguson Braswell Fraser Kubasta PC
- Main IPC: G06F3/0484
- IPC: G06F3/0484 ; G06F3/0488 ; G06F3/0485 ; H03F3/45 ; G09G3/20

Abstract:
An operational amplifier includes an output transistor having a gate coupled to an output node, at least one intermediate transistor each having a common gate node, an input transistor having a gate coupled to an input node, and a load device coupled to sources of the output transistor, the at least one intermediate transistor, and the input transistor. The operational amplifier further includes an output stage coupled to the output node, configured to drive the voltage on the output node based on currents through the output transistor, the at least one intermediate transistors, and the input transistor. The operational amplifier further includes a first switch coupled between the common gate node of the at least one intermediate transistor and the gate of the input transistor, and a second switch coupled between the output node and the common gate node of the at least one intermediate transistors.
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