Invention Grant
- Patent Title: Operation processing circuit and recognition system
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Application No.: US16331727Application Date: 2017-07-04
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Publication No.: US11461684B2Publication Date: 2022-10-04
- Inventor: Hiroaki Sakaguchi
- Applicant: Sony Semiconductor Solutions Corporation
- Applicant Address: JP Kanagawa
- Assignee: Sony Semiconductor Solutions Corporation
- Current Assignee: Sony Semiconductor Solutions Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Michael Best & Friedrich LLP
- Priority: JPJP2016-205451 20161019
- International Application: PCT/JP2017/024422 WO 20170704
- International Announcement: WO2018/074012 WO 20180426
- Main IPC: G06N7/00
- IPC: G06N7/00 ; G06K9/62 ; G06N3/04 ; G06F17/15 ; G06V10/94 ; G06N3/063 ; G06V10/44

Abstract:
Parallel processing suitable for convolution operation in a convolutional neural network is executed.
Each of a plurality of selectors sequentially selects data, which is held in a two-dimensional shift register, in predetermined two-dimensional regions at least partially different from each other. Each of a plurality of two-dimensional convolution operation circuits multiplies the data selected by the corresponding selector by coefficient data stored in a coefficient memory and accumulates results of the multiplication to calculate, in parallel, two-dimensional convolution operation results in the two-dimensional regions. Each of a plurality of adder circuits adds operation results of the two-dimensional convolution operation circuits in a channel direction to output a three-dimensional convolution operation result.
Each of a plurality of selectors sequentially selects data, which is held in a two-dimensional shift register, in predetermined two-dimensional regions at least partially different from each other. Each of a plurality of two-dimensional convolution operation circuits multiplies the data selected by the corresponding selector by coefficient data stored in a coefficient memory and accumulates results of the multiplication to calculate, in parallel, two-dimensional convolution operation results in the two-dimensional regions. Each of a plurality of adder circuits adds operation results of the two-dimensional convolution operation circuits in a channel direction to output a three-dimensional convolution operation result.
Public/Granted literature
- US20190205780A1 OPERATION PROCESSING CIRCUIT AND RECOGNITION SYSTEM Public/Granted day:2019-07-04
Information query
IPC分类:
G | 物理 |
G06 | 计算;推算或计数 |
G06N | 基于特定计算模型的计算机系统 |
G06N7/00 | 基于特定数学模式的计算机系统 |