Operation processing circuit and recognition system
Abstract:
Parallel processing suitable for convolution operation in a convolutional neural network is executed.
Each of a plurality of selectors sequentially selects data, which is held in a two-dimensional shift register, in predetermined two-dimensional regions at least partially different from each other. Each of a plurality of two-dimensional convolution operation circuits multiplies the data selected by the corresponding selector by coefficient data stored in a coefficient memory and accumulates results of the multiplication to calculate, in parallel, two-dimensional convolution operation results in the two-dimensional regions. Each of a plurality of adder circuits adds operation results of the two-dimensional convolution operation circuits in a channel direction to output a three-dimensional convolution operation result.
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