Invention Grant
- Patent Title: Integrated circuit and method of performing a BIST procedure
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Application No.: US17301723Application Date: 2021-04-13
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Publication No.: US11463182B2Publication Date: 2022-10-04
- Inventor: Christophe Athanassiou , Jerome Mallet , Estelle Nguyen
- Applicant: NXP USA, Inc.
- Applicant Address: US TX Austin
- Assignee: NXP USA, Inc.
- Current Assignee: NXP USA, Inc.
- Current Assignee Address: US TX Austin
- Priority: EP20305491 20200513
- Main IPC: H04B17/00
- IPC: H04B17/00 ; H04B17/29 ; G01R31/28 ; H01P5/16 ; H04B1/16

Abstract:
An integrated circuit and a method of performing a built-in-self-test (BIST) procedure in an integrated circuit. The integrated circuit includes a plurality of radio circuits and a switching network for performing a built-in-self-test (BIST) procedure. The switching network includes a plurality of combiners, a plurality of transmitter connection switches, a combiner switch, a splitter switch, a plurality of splitters and a plurality of receiver connection switches. The switching network may also include a splitter bypass switch and/or a combiner bypass switch. The components of the switching network may operate to route signals between outputs and inputs of the radio circuit to implement the built-in-self-test procedure in one or more modes involving either parallel or sequential testing of the components of the radio circuits. A diagnostic mode is also envisaged.
Public/Granted literature
- US20210359773A1 INTEGRATED CIRCUIT AND METHOD OF PERFORMING A BIST PROCEDURE Public/Granted day:2021-11-18
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