Invention Grant
- Patent Title: Fuse lines and plugs for semiconductor devices
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Application No.: US16464565Application Date: 2016-12-30
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Publication No.: US11476190B2Publication Date: 2022-10-18
- Inventor: Balijeet S. Bains , Charles H. Wallace , Zhanping Chen
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2016/069532 WO 20161230
- International Announcement: WO2018/125223 WO 20180705
- Main IPC: H01L23/52
- IPC: H01L23/52 ; H01L23/525 ; H01L21/02 ; H01L21/768 ; H01L23/528 ; H01L23/532

Abstract:
Embodiments herein describe techniques for fuse lines and plugs formation. A semiconductor device may include a fuse line having a nominal fuse segment abutted to a necked fuse segment. The nominal fuse segment may be wider than the necked fuse segment. A first spacer may be along a first side of the fuse line and a second spacer along a second side opposite to the first side of the fuse line. The first spacer may include a part having a width at least twice a width of a part of the second spacer. A plug within a vicinity of the necked fuse segment may have a plug width that may be at least twice a plug with of a plug of an interconnect line outside the vicinity. Other embodiments may also be described and claimed.
Public/Granted literature
- US20210104459A1 FUSE LINES AND PLUGS FOR SEMICONDUCTOR DEVICES Public/Granted day:2021-04-08
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