Invention Grant
- Patent Title: High power positive logic switch
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Application No.: US17141706Application Date: 2021-01-05
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Publication No.: US11476849B2Publication Date: 2022-10-18
- Inventor: Payman Shanjani
- Applicant: pSemi Corporation
- Applicant Address: US CA San Diego
- Assignee: pSemi Corporation
- Current Assignee: pSemi Corporation
- Current Assignee Address: US CA San Diego
- Agency: Jaquez Land Greenhaus & McFarland LLP
- Agent John Land, Esq.
- Main IPC: H03K17/687
- IPC: H03K17/687 ; H03K19/017

Abstract:
A positive-logic FET switch stack that does not require a negative bias voltage, and which can withstand application of a high voltage RF signal without requiring terminal capacitors. Some embodiments include a stack of FET switches, with at least one FET requiring a negative VGS to turn OFF and configured so as to not require a negative voltage, series-coupled on at least one end to an end-cap FET that turns OFF when the VGS of such end-cap FET is essentially zero volts, wherein at least one end-cap FET is configured to be coupled to a corresponding RF signal source and has a gate coupled to the corresponding RF signal source through an associated switch circuit. The switch circuit may include an NMOSFET and a PMOSFET, or a diode and an NMOSFET, or a diode and an NMOSFET and a PMOSFET.
Public/Granted literature
- US20210211127A1 High Power Positive Logic Switch Public/Granted day:2021-07-08
Information query
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