Invention Grant
- Patent Title: Vertical transistor having bottom spacers on source/drain regions with different heights along junction region
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Application No.: US17136852Application Date: 2020-12-29
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Publication No.: US11482612B2Publication Date: 2022-10-25
- Inventor: Shogo Mochizuki , Kangguo Cheng , Juntao Li , Choonghyun Lee
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Ryan, Mason & Lewis, LLP
- Agent Randall Bluestone
- Main IPC: H01L29/786
- IPC: H01L29/786 ; H01L29/66 ; H01L21/8234 ; H01L21/02 ; H01L21/225 ; H01L21/8238

Abstract:
A method for manufacturing a semiconductor device includes forming a plurality of fins on a semiconductor substrate. In the method, sacrificial spacer layers are formed on the plurality of fins, and portions of the semiconductor substrate located under the sacrificial spacer layers and located at sides of the plurality of fins are removed. Bottom source/drain regions are grown in at least part of an area where the portions of the semiconductor substrate were removed, and sacrificial epitaxial layers are grown on the bottom source/drain regions. The method also includes diffusing dopants from the bottom source/drain regions and the sacrificial epitaxial layers into portions of the semiconductor substrate under the plurality of fins. The sacrificial epitaxial layers are removed, and bottom spacers are formed in at least part of an area where the sacrificial epitaxial layers were removed.
Public/Granted literature
- US20210119020A1 BOTTOM SPACER STRUCTURE FOR VERTICAL FIELD EFFECT TRANSISTOR AND METHOD OF FORMING SAME Public/Granted day:2021-04-22
Information query
IPC分类: