Invention Grant
- Patent Title: Non-volatile memory die with on-chip data augmentation components for use with machine learning
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Application No.: US16447619Application Date: 2019-06-20
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Publication No.: US11501109B2Publication Date: 2022-11-15
- Inventor: Alexander Bazarsky , Ariel Navon
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Loza & Loza, LLP
- Agent Gabriel Fitch
- Main IPC: G06F11/10
- IPC: G06F11/10 ; G06K9/62 ; G06V10/82 ; G06V10/94 ; G06N3/08 ; G11C16/04 ; G06T3/00 ; G06N20/00 ; G06F11/07 ; G11C16/26 ; G06T3/60

Abstract:
Methods and apparatus are disclosed for implementing machine learning data augmentation within the die of a non-volatile memory (NVM) apparatus using on-chip circuit components formed on or within the die. Some particular aspects relate to configuring under-the-array or next-to-the-array components of the die to generate augmented versions of images for use in training a Deep Learning Accelerator of an image recognition system by rotating, translating, skewing, cropping, etc., a set of initial training images obtained from a host device. Other aspects relate to configuring under-the-array or next-to-the-array components of the die to generate noise-augmented images by, for example, storing and then reading training images from worn regions of a NAND array to inject noise into the images.
Information query