Invention Grant
- Patent Title: Multi-level vertical memory device including inter-level channel connector
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Application No.: US16367305Application Date: 2019-03-28
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Publication No.: US11502094B2Publication Date: 2022-11-15
- Inventor: Ruo Fang Zhang , Enbo Wang , Haohao Yang , Qianbing Xu , Yushi Hu , Qian Tao
- Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
- Applicant Address: CN Wuhan
- Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
- Current Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
- Current Assignee Address: CN Wuhan
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: H01L27/11556
- IPC: H01L27/11556 ; H01L27/11524

Abstract:
A semiconductor device includes a string of transistors stacked along a vertical direction above a substrate of the semiconductor device. The string can include a first substring, a channel connector disposed above the first substring, and a second substring. The first substring includes a first channel structure having a first channel layer and a first gate dielectric structure that extend along the vertical direction. The second substring is stacked above the channel connector, and has a second channel structure that includes a second channel layer and a second gate dielectric structure that extend along the vertical direction. The channel connector, electrically coupling the first and the second channel layer, is disposed below the second gate dielectric structure to enable formation of a conductive path in a bottom region of the second channel layer. The bottom region is associated with a lowermost transistor in the second substring.
Information query
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