Invention Grant
- Patent Title: Stress modulation for dielectric layers
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Application No.: US16933622Application Date: 2020-07-20
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Publication No.: US11502196B2Publication Date: 2022-11-15
- Inventor: Chung-Ting Ko , Han-Chi Lin , Chunyao Wang , Ching Yu Huang , Tze-Liang Lee , Yung-Chih Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/762 ; H01L21/3213 ; H01L21/02 ; H01L21/3115 ; H01L29/66 ; H01L21/3065 ; H01L27/088 ; H01L21/8234
Abstract:
A method includes etching a first portion and a second portion of a dummy gate stack to form a first opening and a second opening, respectively, and depositing a silicon nitride layer to fill the first opening and the second opening. The deposition of the silicon nitride layer comprises a first process selected from treating the silicon nitride layer using hydrogen radicals, implanting the silicon nitride layer, and combinations thereof. The method further includes etching a third portion of the dummy gate stack to form a trench, etching a semiconductor fin underlying the third portion to extend the trench down into a bulk portion of a semiconductor substrate underlying the dummy gate stack, and depositing a second silicon nitride layer into the trench.
Public/Granted literature
- US20200350433A1 Stress Modulation for Dielectric Layers Public/Granted day:2020-11-05
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