A controller for generating a sequence of pulse is disclosed. The controller includes a plurality of pulse width modulation (PWM) modules. Each PWM Module configured to generate a first sequence of pulses and a second sequence of pulses each having a width that is modulated by a PWM value stored in a PWM register of the PWM module. Each PWM module includes two outputs. The first sequence of pulses is outputted on the first output and the second sequence of pulses is outputted on the second output. The controller also includes a memory having a plurality of memory tables and a plurality of direct memory access (DMA) modules. Each memory table configured to store PWM values to be written into the PWM register and each DMA module is coupled to a respective PWM module in the plurality of PWM modules and to a respective memory table in the plurality of memory tables and configured to write a PWM value from the memory table into the PWM register in response to a DMA trigger. The controller further includes a core coupled to the plurality of memory tables and configured to write the PWM values into the plurality of memory tables.