Exemplary aspects disclosed herein include detecting a repetitive pattern in an instruction pipeline of a processor to reduce repeated fetching. The processor includes a pattern record circuit configured to receive information in a data stream (e.g., instructions or consumed data) in the instruction pipeline. The pattern record circuit includes a first in, first out (FIFO) table circuit that contains an input record column and plurality of additional adjacent record columns. As new data occurs in the data stream, the data record circuit is configured to sequentially record next incoming data from the data stream into a next input entry of an input record column and then shift previously recorded data into adjacent entries of adjacent record columns. The distance between the input record column and the additional record column that has matching data is the distance in the data stream between a reoccurrence of data in the data stream.