Invention Grant
- Patent Title: Semiconductor patterning and resulting structures
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Application No.: US17151973Application Date: 2021-01-19
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Publication No.: US11521856B2Publication Date: 2022-12-06
- Inventor: Chun-Ming Lung , ChunYao Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/033
- IPC: H01L21/033 ; H01L21/8234 ; H01L21/308 ; H01L21/02 ; H01L21/3065 ; H01L21/302 ; H01L21/311 ; H01L21/3213

Abstract:
A method includes depositing a hard mask over a target layer. Depositing the hard mask includes depositing a first hard mask layer having a first density and depositing a second hard mask layer over the first hard mask layer, the second hard mask layer having a second density greater than the first density. The method further includes forming a plurality of mandrels over the hard mask; depositing a spacer layer over and along sidewalls of the plurality of mandrels; patterning the spacer layer to provide a plurality of spacers on the sidewalls of the plurality of mandrels; after patterning the spacer layer, removing the plurality of mandrels; transferring a patterning the plurality of spacers to the hard mask; and patterning the target layer using the hard mask as a mask.
Public/Granted literature
- US20220102142A1 SEMICONDUCTOR PATTERNING AND RESULTING STRUCTURES Public/Granted day:2022-03-31
Information query
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