Invention Grant
- Patent Title: Reducing stress cracks in substrates
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Application No.: US17247094Application Date: 2020-11-30
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Publication No.: US11521928B2Publication Date: 2022-12-06
- Inventor: Yong Liu , Stephen St. Germain
- Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Applicant Address: US AZ Phoenix
- Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee Address: US AZ Phoenix
- Agency: Brake Hughes Bellermann LLP
- Main IPC: H01L23/532
- IPC: H01L23/532 ; H01L21/768 ; H01L23/00

Abstract:
Implementations described herein are related to an improved semiconductor device package for providing an electrical connection between one or more semiconductor die and one or more substrates. The one or more substrates includes a dielectric layer having a first side and a second side opposite the first side, and a first metal layer bonded to the first side of the dielectric layer, the first metal layer having a first portion and a second portion. The semiconductor device package can also include a semiconductor die disposed onto the first metal layer within the first portion of the first metal layer. In some implementations, the one or more conducting substrates includes a direct bonded copper (DBC) substrate, i.e., the metal is copper.
Public/Granted literature
- US20220173049A1 REDUCING STRESS CRACKS IN SUBSTRATES Public/Granted day:2022-06-02
Information query
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