Invention Grant
- Patent Title: High performance multi-dimensional device and logic integration
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Application No.: US17097146Application Date: 2020-11-13
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Publication No.: US11521972B2Publication Date: 2022-12-06
- Inventor: Mark I. Gardner , H. Jim Fulford
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L29/06 ; H01L29/423 ; H01L29/786 ; H01L21/02 ; H01L21/8238 ; H01L29/66

Abstract:
A semiconductor device is provided. The semiconductor device can include a bottom substrate, a device plane over the bottom substrate, a dielectric layer over the device plane, localized substrates over the dielectric layer, and semiconductor devices over the localized substrates. The localized substrates can be separated from each other along a top surface of the bottom substrate. A method of microfabrication is provided. The method can include forming a target layer over a bottom substrate where the target layer includes one or more localized regions that include one or more semiconductor materials. The method can also include performing a thermal process to change crystal structures of the one or more localized regions of the target layer. The method can further include forming semiconductor devices over the localized regions of the target layer.
Public/Granted literature
- US20210343714A1 HIGH PERFORMANCE MULTI-DIMENSIONAL DEVICE AND LOGIC INTEGRATION Public/Granted day:2021-11-04
Information query
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