Invention Grant
- Patent Title: Multilayer circuit board manufacturing method
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Application No.: US16463552Application Date: 2017-11-24
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Publication No.: US11527415B2Publication Date: 2022-12-13
- Inventor: Yoshinori Matsuura , Tetsuro Sato , Takenori Yanai , Toshimi Nakamura
- Applicant: MITSUI MINING & SMELTING CO., LTD.
- Applicant Address: JP Tokyo
- Assignee: MITSUI MINING & SMELTING CO., LTD.
- Current Assignee: MITSUI MINING & SMELTING CO., LTD.
- Current Assignee Address: JP Tokyo
- Agency: Greenblum & Bernstein, P.L.C.
- Priority: JPJP2016-230539 20161128
- International Application: PCT/JP2017/042288 WO 20171124
- International Announcement: WO2018/097264 WO 20180531
- Main IPC: H01L21/48
- IPC: H01L21/48 ; H01L21/683 ; H01L23/498 ; H01L23/31

Abstract:
There is provided a method of manufacturing a multilayer wiring board including: alternately stacking wiring layers and insulating layers; stacking a reinforcing sheet having openings on one surface of the resulting multilayer laminate with a soluble adhesive layer therebetween; contacting or infiltrating the soluble adhesive layer with a liquid capable of dissolving the soluble adhesive layer through the openings to thereby dissolve or soften the soluble adhesive layer; and releasing the reinforcing sheet from the multilayer laminate at the position of the soluble adhesive layer. This method enables the multilayer wiring layer to be reinforced so as to generate no large local warpage, thereby improving the reliable connection in the multilayer wiring layer and the flatness (coplanarity) on the surface of the multilayer wiring layer. The reinforcing sheet having finished its role can be released in a significantly short time, while minimizing the stress applied to the multilayer laminate.
Information query
IPC分类: