Invention Grant
- Patent Title: Integrated circuit test method and structure thereof
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Application No.: US17195537Application Date: 2021-03-08
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Publication No.: US11532524B2Publication Date: 2022-12-20
- Inventor: Hsien-Wen Liu , Hsien-Wei Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/66
- IPC: H01L21/66 ; H01L23/00
Abstract:
A device includes a semiconductor die. The semiconductor die includes a device layer, an interconnect layer over the device layer, a conductive pad over the interconnect layer, a conductive seed layer directly on the conductive pad, and a passivation layer encapsulating the conductive pad and the conductive seed layer.
Public/Granted literature
- US20220028748A1 INTEGRATED CIRCUIT TEST METHOD AND STRUCTURE THEREOF Public/Granted day:2022-01-27
Information query
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