Invention Grant
- Patent Title: Integrated circuit package and method
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Application No.: US16882132Application Date: 2020-05-22
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Publication No.: US11532533B2Publication Date: 2022-12-20
- Inventor: Chen-Hua Yu , Wei Ling Chang , Chuei-Tang Wang , Fong-yuan Chang , Chieh-Yen Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L23/31 ; H01L23/00

Abstract:
In an embodiment, a device includes: a processor die including circuit blocks, the circuit blocks including active devices of a first technology node; a power gating die including power semiconductor devices of a second technology node, the second technology node larger than the first technology node; and a first redistribution structure including first metallization patterns, the first metallization patterns including power supply source lines and power supply ground lines, where a first subset of the circuit blocks is electrically coupled to the power supply source lines and the power supply ground lines through the power semiconductor devices, and a second subset of the circuit blocks is permanently electrically coupled to the power supply source lines and the power supply ground lines.
Public/Granted literature
- US20210118759A1 Integrated Circuit Package and Method Public/Granted day:2021-04-22
Information query
IPC分类: