Invention Grant
- Patent Title: Capacitor die for stacked integrated circuits
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Application No.: US16870176Application Date: 2020-05-08
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Publication No.: US11532592B2Publication Date: 2022-12-20
- Inventor: David C. Zhang , Pranav Balachander
- Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
- Applicant Address: US CA San Jose
- Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
- Current Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
- Current Assignee Address: US CA San Jose
- Agency: Vierra Magen Marcus LLP
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/538 ; H01L23/66 ; H05K1/02 ; H01L23/522

Abstract:
An apparatus is provided that includes a die stack having a first die and a second die disposed above a substrate, and a capacitor die disposed in the die stack between the first die and the second die. The capacitor die includes a plurality of integrated circuit capacitors that are configured to be selectively coupled together to form a desired capacitor value coupled to at least one of the first die and the second die.
Public/Granted literature
- US20210351152A1 CAPACITOR DIE FOR STACKED INTEGRATED CIRCUITS Public/Granted day:2021-11-11
Information query
IPC分类: