Invention Grant
- Patent Title: Reduction of gate-drain capacitance
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Application No.: US16888537Application Date: 2020-05-29
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Publication No.: US11532626B2Publication Date: 2022-12-20
- Inventor: Jung-Hung Chang , Lo-Heng Chang , Zhi-Chang Lin , Shih-Cheng Chen , Kuo-Cheng Chiang , Chih-Hao Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L27/092 ; H01L21/02 ; H01L21/8238 ; H01L29/08 ; H01L29/66 ; H01L29/10
Abstract:
A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.
Public/Granted literature
- US20210375864A1 REDUCTION OF GATE-DRAIN CAPACITANCE Public/Granted day:2021-12-02
Information query
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