Invention Grant
- Patent Title: Semiconductor device having vertical DMOS and manufacturing method thereof
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Application No.: US17150114Application Date: 2021-01-15
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Publication No.: US11532741B2Publication Date: 2022-12-20
- Inventor: Hyun Kwang Shin
- Applicant: KEY FOUNDRY CO., LTD.
- Applicant Address: KR Cheongju-si
- Assignee: KEY FOUNDRY CO., LTD.
- Current Assignee: KEY FOUNDRY CO., LTD.
- Current Assignee Address: KR Cheongju-si
- Agency: NSIP Law
- Priority: KR10-2020-0104613 20200820
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L27/092 ; H01L29/423
Abstract:
A semiconductor device includes a substrate, a buried doped layer formed on the substrate, a trench gate formed on the buried doped layer, a source region formed adjacent the trench gate, an interlayer dielectric layer formed on the trench gate and the source region, a source contact plug formed to extend and connect to the source region, and a drain contact plug, extending and connecting to the buried doped layer, formed deeper than the source contact plug.
Public/Granted literature
- US20220059689A1 SEMICONDUCTOR DEVICE HAVING VERTICAL DMOS AND MANUFACTURING METHOD THEREOF Public/Granted day:2022-02-24
Information query
IPC分类:
