Invention Grant
- Patent Title: Semiconductor package having molded die and semiconductor die and manufacturing method thereof
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Application No.: US17144061Application Date: 2021-01-07
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Publication No.: US11538761B2Publication Date: 2022-12-27
- Inventor: Hao-Cheng Hou , Wei-Yu Chen , Jung-Wei Cheng , Tsung-Ding Wang , Chien-Hsun Lee , Chung-Shi Liu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L23/00 ; H01L23/31 ; H01L21/56 ; H01L25/18

Abstract:
A semiconductor package includes a first semiconductor die, a molded die, a third encapsulant, and a redistribution structure. The molded die includes a chip, a first encapsulant, and a second encapsulant. The first encapsulant laterally wraps the chip. The second encapsulant laterally wraps the first encapsulant. The third encapsulant laterally wraps the first semiconductor die and the molded die. The redistribution structure extends on the second encapsulant, the third encapsulant, and the first semiconductor die. The redistribution structure is electrically connected to the first semiconductor die and the molded die. The second encapsulant separates the first encapsulant from the third encapsulant.
Public/Granted literature
- US20220216153A1 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF Public/Granted day:2022-07-07
Information query
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