Invention Grant
- Patent Title: Integrated circuitry, a method used in forming integrated circuitry, and a method used in forming a memory array comprising strings of memory cells
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Application No.: US16930843Application Date: 2020-07-16
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Publication No.: US11538819B2Publication Date: 2022-12-27
- Inventor: Purnima Narayanan
- Applicant: Micron Technology, inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, inc.
- Current Assignee: Micron Technology, inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L27/11556 ; H01L25/065 ; H01L21/50 ; G11C5/02 ; G11C5/06 ; H01L27/11582
Abstract:
A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The first tiers comprise doped silicon dioxide and the second tiers comprise undoped silicon dioxide. Horizontally-elongated trenches are formed into the stack. Through the trenches, the doped silicon dioxide that is in the first tiers is etched selectively relative to the undoped silicon dioxide that is in the second tiers. Conducting material is formed in the void space in the first tiers that is left by the etching. Structure independent of method is disclosed.
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