Memory might include an array of memory cells having a plurality of strings of series-connected split-gate memory cells each including a primary memory cell portion and an assist memory cell portion, a plurality of primary access lines each connected to a control gate of the primary memory cell portion of a respective split-gate memory cell of each string of series-connected split-gate memory cells of the plurality of strings of series-connected split-gate memory cells, and a plurality of assist access lines each connected to a control gate of the assist memory cell portion of its respective split-gate memory cell of each string of series-connected split-gate memory cells of the plurality of strings of series-connected split-gate memory cells.