Invention Grant
- Patent Title: III-V compound semiconductor dies with stress-treated inactive surfaces to avoid packaging-induced fractures, and related methods
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Application No.: US16868147Application Date: 2020-05-06
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Publication No.: US11545404B2Publication Date: 2023-01-03
- Inventor: Gengming Tao , Bin Yang , Xia Li
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: W&T
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L21/56 ; H01L21/78 ; H01L23/00

Abstract:
Before a semiconductor die of a brittle III-V compound semiconductor is encapsulated with a molding compound during package fabrication, side surfaces of the semiconductor die are treated to avoid or prevent surface imperfections from propagating and fracturing the crystal structure of the substrate of the III-V compound semiconductor under the stresses applied as the molding compound solidifies. Surfaces are treated to form a passivation layer, which may be a passivated layer of the substrate or a passivation material on the substrate. In a passivated layer, imperfections of an external layer are transformed to be less susceptible to fracture. Passivation material, such as a poly-crystalline layer on the substrate surface, diffuses stresses that are applied by the molding compound. Semiconductor dies in flip-chip and wire-bond chip packages with treated side surfaces as disclosed have a reduced incidence of failure caused by die fracturing.
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