Invention Grant
- Patent Title: Interconnect structures having lines and vias comprising different conductive materials
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Application No.: US17036543Application Date: 2020-09-29
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Publication No.: US11545429B2Publication Date: 2023-01-03
- Inventor: Sung-Li Wang , Yasutoshi Okuno
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L23/528 ; H01L21/768 ; H01L23/532

Abstract:
Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.
Public/Granted literature
- US20210013146A1 Interconnect Structures and Methods of Forming the Same Public/Granted day:2021-01-14
Information query
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