Invention Grant
- Patent Title: Active suppression circuitry
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Application No.: US16877123Application Date: 2020-05-18
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Publication No.: US11545968B1Publication Date: 2023-01-03
- Inventor: Moo Sung Chae , Thomas Evan Wilson
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H03K5/1252
- IPC: H03K5/1252 ; G11C5/14 ; H03H7/06 ; H03F3/45

Abstract:
Various embodiments provide for active suppression circuitry. The active suppression circuitry can be used with a circuit for a memory system, such as a dual data rate (DDR) memory system. For example, some embodiments provide an active suppression integrated circuit. The active suppression integrated circuit can be used by a memory system to efficiently suppress power supply noise caused by resonance of a power delivery network (PDN) of the memory system, thereby improving power integrity of the memory system input/output.
Information query
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