Invention Grant
- Patent Title: Scan architecture for interconnect testing in 3D integrated circuits
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Application No.: US16724787Application Date: 2019-12-23
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Publication No.: US11549984B2Publication Date: 2023-01-10
- Inventor: Sandeep Kumar Goel , Yun-Han Lee , Saman M. I. Adham , Marat Gershoig
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Duane Morris LLP
- Main IPC: G01R31/3177
- IPC: G01R31/3177 ; G01R31/3185 ; G01R31/28 ; G01R31/317

Abstract:
In one embodiment, a device comprises: a first die having disposed thereon a first plurality of latches wherein ones of the first plurality of latches are operatively connected to an adjacent one of the first plurality of latches; and a second die having disposed thereon a second plurality of latches wherein ones of the second plurality of latches are operatively connected to an adjacent one of the second plurality of latches. Each latch of the first plurality of latches on said first die corresponds to a latch in the second plurality of latches on said second die. Each set of corresponding latches are operatively connected. A scan path comprises a closed loop comprising each of said first and second plurality of latches. One of the second plurality of latches is operatively connected to another one of the second plurality of latches via an inverter.
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