Invention Grant
- Patent Title: Delay calibration for a stepped frequency continuous wave digital signal chain
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Application No.: US16930452Application Date: 2020-07-16
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Publication No.: US11550029B2Publication Date: 2023-01-10
- Inventor: Vinoth Kumar , Satishchandra G. Rao , Corey Petersen , Madhusudan Rathi , Gerard E. Taylor , Kaustubh Mundhada
- Applicant: Analog Devices International Unlimited Company
- Applicant Address: IE Limerick
- Assignee: Analog Devices International Unlimited Company
- Current Assignee: Analog Devices International Unlimited Company
- Current Assignee Address: IE Limerick
- Agency: Akona IP PC
- Main IPC: G01S7/40
- IPC: G01S7/40 ; G01S13/32 ; G01S7/10

Abstract:
Delay calibration for digital signal chains of SFCW systems is disclosed. An example calibration method includes receiving a burst with a test pulse, the burst having a duration of L clock cycles; receiving a trigger indicative of a time when the burst was transmitted; generating a digital signal indicative of the received burst; for each of L clock cycles, computing a moving average of a subset of digital samples and an amplitude for each average; identifying one moving average for which the computed amplitude is closest to an expected amplitude; identifying the clock cycle of the identified moving average; and updating at least one delay to be applied in digital signal processing of received bursts based on a difference between the trigger and the identified clock cycle. The delay may be used for selecting digital samples of the received signal that contain valid data for performing further data processing.
Public/Granted literature
- US20220018931A1 DELAY CALIBRATION FOR A STEPPED FREQUENCY CONTINUOUS WAVE DIGITAL SIGNAL CHAIN Public/Granted day:2022-01-20
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